1. Field of the Invention
The present application generally relates to device under test (DUT) arrays and, more particularly, to a layout for DUT arrays used to detect defects during semiconductor wafer manufacturing.
2. Description of Related Art
To assist in evaluating and/or controlling a semiconductor fabrication process, integrated circuit devices are formed on a wafer for the purpose of electrically testing these devices, which are referred to as devices under test (DUTs), using a wafer tester. Typically, a wafer with DUTs formed thereon is positioned within a wafer tester. The wafer tester has an array of probes that make electrical contact with contact pads for the DUTs on the wafer. The wafer tester then performs electrical testing of the DUTs. Random defects (e.g., particles or the like) can cause electrically measurable faults (killer defects), which are dependent on the chip layout as well as the layer and location of the defects.
Also, certain layout geometries can cause systematic faults dependent on specific combinations of layout and manufacturing process steps. Random as well as systematic faults are responsible for manufacturing related malfunction of chips. Thus, investigating random and systematic faults is important for yield enhancement and to control the quality of process steps and resulting product chips. Several of these concerns are discussed in Staper, C. H., Rosner, R. J., “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation,” IEEE Transactions on Semiconductor Manufacturing, pp. 95-102, Vol. 8, No. 2, 1995, which is incorporated by reference herein. Test structures, therefore, are used to detect faults, to identify and localize defects, as well as to characterize systematic manufacturability of layout geometries
Many test structures types that use via or contact chains, snake and comb lines etc. have been described to detect defects, e.g. in Ipri, A. C., Sarace, J. C., “Integrated Circuit Process and Design Rule Evaluation Techniques,” RCA Review, pp. 323-350, Volume 38, Number 3, September 1977, and Buehler, M. G., “Microelectronic Test Chips for VLSI Electronics,” VLSI Electronics Microstructure Science, pp. 529-576, Vol 9, Chapter 9, Academic Press, 1983, both of which are incorporated by reference herein.
Two parallel via chains are described in Doong, Kelvin, Cheng, J., Hsu, C., “Design and Simulation of Addressable Fault Site Test Structure for IC Process Control Monitor,” International Symposium on Semiconductor Manufacturing, 1999, which is incorporated herein by reference.
For all these test structures, the resistance over the DUT has to be measured. For that, a so called “Four Terminal Resistance Measurement” is executed, as shown in FIGS. 2-32 and 3-15 of “6th Edition: Low Level Measurements Handbook”, Keithley Instruments Inc., pp. 2-39 & 3-18, 2004, which is incorporated herein by reference. On page C-4, the measurement is described as “A measurement where two leads are used to supply a current to an unknown, and two different leads are used to sense the voltage drop across the resistance.” In this manner, the resistance can be measured for snakes, combs, via chains and parallel devices as mentioned earlier.
FIG. 1 illustrates a simplified example of a circuit 100 used to test a DUT 110 using a 4-Terminal Measurement Points (4-TMP) scheme. As shown, the circuit 100 includes TMP1 and TMP3 coupled to an end of the DUT 110 and respectively to resistor 102 and resistor 106. TMP2 and TMP4 are coupled to another end of the DUT 110 and respectively to resistor 104 and resistor 108. A voltage source is coupled to resistor 102, and which leads to TMP1. A voltage meter is coupled between TMP3 and TMP4, through resistors 106 and 108, respectively. A current meter is coupled to resistor 104, which links to TMP2. The circuit 100, therefore represents a schematic embodiment for testing four terminal resistance performance of DUT 110. However, DUT 110 of FIG. 1 is only one DUT, and to test additional DUTs, other logic would be needed to enable addressing.
FIG. 2 illustrates an example where the circuit 100 of FIG. 1 is modified, so that transmission gates 122 are used in circuit 120. The use of transmission gates is known, but as can be appreciated, the use of transmission gates 122a-122d, to address/select DUT 110, will add a substantial number of transistors. In circuit 120, eight (8) transistors are needed to enable specific access to DUT 110, when conducting a 4-TMP testing scheme. Although it is possible to conduct testing of DUT 110, it should be appreciated many performance tests will require testing of many DUTs 110, either individually or in series. Consequently, each DUT 110, using the circuitry of FIG. 2, will require 8 transistors. The area on a chip needed to layout the 8 selection transistors, as can be expected, will be large. For this reason, only small DUT 110 arrays are possible with know selection transistor schemes. This places a limit on the number of DUTs and the data that can be obtained from specific testing.
All test structures mentioned above are usually connected to individual terminal or pads for testing. In some cases, far more than 1000 differently designed test structures per layer may be required to achieve yield and performance improvements, as described in detail in U.S. Pat. Nos. 6,449,749 and 6,901,564, entitled: System and Method for Product Yield Prediction, both of which are incorporated by reference herein. With the demand for more dense and compact placement of DUTs, it can be appreciated that the circuit 120 scheme of the prior art places significant constraints on testing structures and algorithms.
For detecting a completely failing test structure, where its measured resistance is many orders of magnitude different from its expected value, it is fine to use large area test structures. The large area for a single DUT might be in the order of ±100 um by 100 um. However, so called “soft failing” events have become more severe in semiconductor manufacturing, where just a small fraction of a test structure changes its local resistance by as little as one order of magnitude compared to its expected value. Detecting such soft fails requires access to smaller test structure segments, since a soft fail will not be detectable within a single large area test structure. Further, it is difficult or impossible to place all those thousands of small test structures on a single test chip if they are all connected to individual pads for testing, since there is not enough area to place all pads. Further, because of the large size of prior art DUTs, many times it is not possible to perform localization (e.g., to find the failing DUT in an array) nor to perform analysis of soft fails.
In view of the forgoing, there is a need for circuits that enable accurate four terminal measurement point (4-TMP) analysis of DUTs, where the access circuitry to each DUT uses compact logic that minimizes area layout, thus enabling densely arranged DUT arrays for complex 4-TMP processing of DUT performance parameters.